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CS5466
Low Cost Power/Energy IC with Pulse Output
Features
Single Chip; Power Measurement Solution Energy Data Linearity: 0.1% of Reading over 1000:1 Dynamic Range On-Chip functions: Measures Energy and Performs Energy-to-Pulse Conversions Meets Accuracy Spec for IEC 687/1036 High Pass Filter Option Four Input Ranges for Current Channel On-Chip 2.5 V Reference (25 ppm/C typ) Pulse Outputs for Stepper Motor or Mechanical Counter On-Chip Energy Direction Indicator Ground Referenced Input Signals with Single Supply High Frequency Output for Calibration On-Chip Power-on Reset Power Supply Configurations:
VA+ = +5 V; AGND = 0 V; VD+ = +3.3 V to 5 V
I
Description
The CS5466 is a low cost power meter solution combining two Analog-to-Digital Converters (ADC)'s, an energy-to-frequency converter, and energy pulse outputs on a single chip. It is designed to accurately measure and calculate energy for single phase 2- or 3wire power metering applications with minimal external components. Low frequency energy outputs, E1 and E2, supply average real power and can be used to drive a stepper motor or a mechanical counter; the high frequency energy output FOUT can be used for calibration; and NEG indicates negative power. The CS5466 has configuration pins which allow for direct configuration of pulse output frequency, current channel input range, and high pass filter enable option. The CS5466 also has a power-on reset function which holds the part in reset until the supply reaches an operable level. ORDERING INFORMATION
CS5466-ISZ -40 to 85 C 24-pin SSOP Lead Free
VA+ PGA: x10, x50, x100, x150 IIN+ IIN+ 4th Order Modulator
RESET
HPF
VD+
Digital Filter
HPF
Option
FOUT Energy-toFrequency Conversion Negative Power Indication E1 E2 NEG FREQ0 FREQ1 FREQ2
IGAIN0 IGAIN1
VREFIN
x1
VIN+ VIN-
+ x10 -
2nd Order Modulator
Digital Filter
HPF
Option
CPUCLK VREFOUT 2.5V On-Chip Reference Clock Generator XOUT XIN
AGND
DGND
Preliminary Product Information
http://www.cirrus.com
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright Cirrus Logic, Inc. 2004 (All Rights Reserved)
(c)
OCT `04 DS659PP2 1
CS5466
TABLE OF CONTENTS
1. GENERAL DESCRIPTION ....................................................................................................... 3 2. PIN DESCRIPTION ................................................................................................................... 4 3. CHARACTERISTICS/SPECIFICATIONS ................................................................................. 5 RECOMMENDED OPERATING CONDITIONS ....................................................................... 5 ANALOG CHARACTERISTICS ................................................................................................ 5 VOLTAGE REFERENCE.......................................................................................................... 6 DIGITAL CHARACTERISTICS ................................................................................................. 7 SWITCHING CHARACTERISTICS .......................................................................................... 8 ABSOLUTE MAXIMUM RATINGS ........................................................................................... 9 4. THEORY OF OPERATION ..................................................................................................... 10 4.1 Digital Filters .................................................................................................................... 10 4.2 Average Real Power Computation ................................................................................... 10 5. FUNCTIONAL DESCRIPTION ............................................................................................... 11 5.1 Analog Inputs ................................................................................................................... 11 5.1.1 Voltage Channel .................................................................................................. 11 5.1.2 Current Channel .................................................................................................. 11 5.2 High-Pass Filter ............................................................................................................... 11 5.3 Energy Pulse Outputs ...................................................................................................... 11 5.3.1 Pulse Output Format. .......................................................................................... 11 5.3.2 Selecting Frequency of E1 and E2 ...................................................................... 11 5.3.3 Selecting Frequency of FOUT ............................................................................. 12 5.3.4 Absolute Max Frequency on E1 and E2 .............................................................. 12 5.3.5 E1 and E2 Frequency Calculation ....................................................................... 12 5.4 Energy Direction Indicator ............................................................................................... 13 5.5 Power-on Reset ............................................................................................................... 13 5.6 Oscillator Characteristics ................................................................................................. 13 5.7 Basic Application Circuit .................................................................................................. 13 6. PACKAGE DIMENSIONS ....................................................................................................... 15 7. REVISIONS ............................................................................................................................ 16
LIST OF FIGURES
Figure 1. Timing Diagram for E1, E2 and FOUT ............................................................................. 8 Figure 2. Data Flow ....................................................................................................................... 10 Figure 3. Oscillator Connection ..................................................................................................... 13 Figure 4. Typical Connection Diagram .......................................................................................... 14
LIST OF TABLES
Table 1. Current Channel PGA Setting ......................................................................................... 11 Table 2. Maximum Frequency for E1, E2 and FOUT ................................................................... 12 Table 3. Absolute Max Frequency on E1 and E2.......................................................................... 12
2
CS5466
1. GENERAL DESCRIPTION
The CS5466 is a CMOS monolithic power measurement device with an energy computation engine. The CS5466 combines a programmable gain amplifier, two ADC's and energy-to-frequency conversion circuitry on a single chip. The CS5466 is designed for energy measurement applications and is optimized to interface to a shunt or current transformer for current measurement, and to a resistive divider or transformer for voltage measurement. The current channel has a programmable gain amplifier (PGA) which provides four full-scale input options. With a single +5 V supply on VA+/AGND, both of the CS5466's input channels accommodate common mode + signal levels between (AGND - 0.25 V) and VA+. The CS5466 has three pulse output pins: E1, E2 and FOUT. E1 and E2 can be used to directly drive a mechanical counter or stepper motor, or interface to a micro controller. The FOUT pin conveys average real power at a pulse frequency many times higher than that of the E1 or E2 pulse frequency, allowing for high speed calibration.
3
CS5466
2. PIN DESCRIPTION
XOUT CPUCLK VD+ DGND IGAIN0 NEG IGAIN1 HPF VIN+ VINVREFOUT VREFIN 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 XIN FREQ0 E1 E2 FREQ1 RESET FOUT FREQ2 IIN+ IINVA+ AGND Crystal In Frequency Select 0 Energy Output 1 Energy Output 2 Frequency Select 1 Reset High Frequency Output Frequency Select 2 Differential Current Input Differential Current Input Positive Analog Supply Analog Ground
Crystal Out CPU Clock Output Positive Power Supply Digital Ground Gain Select 0 Negative Energy Indicator Gain Select 1 High Pass Filter Enable Differential Voltage Input Differential Voltage Input Voltage Reference Output Voltage Reference Input
Clock Generator
Crystal Out Crystal In CPU Clock Output
1, 24
XOUT, XIN - A single stage amplifier inside the chip is connected to these pins and can be used with a crystal to provide the system clock for the device. Alternatively, an external clock can be supplied to the XIN pin to provide the system clock for the device. CPUCLK - Output of on-chip oscillator which can drive one standard CMOS load.
2
Control Pins
Gain Select Frequency Select High Pass Filter Enable Reset 5, 7
IGAIN1, IGAIN0 - Used to select the current channel input gain range.
17, 20, 23 FREQ2,FREQ1,FREQ0 - Used to select max pulse output frequency for E1, E2, and FOUT. 8 19
HPF - High disables the HPF. Low activates HPF on Voltage channel. Connecting HPF pin to FOUT pin activates HPF on Current channel. RESET - Low activates Reset.
Energy Pulse Outputs
Energy Output High Freq Output Neg Energy Indicator 21, 22 18 6
E1, E2 - Active low alternating pulses with an output frequency that is proportional to the average real power. FOUT - Outputs energy pulses at a frequency higher than E1 and E2 outputs. Used for calibration purposes. NEG - High indicates negative energy.
Analog Inputs/Outputs
Differential Voltage Inputs Voltage Reference Output Voltage Reference Input Differential Current Inputs 9, 10 11 12 16, 15
VIN+, VIN- - Differential analog input pins for voltage channel. VREFOUT - The on-chip voltage reference output pin. The voltage reference has a nominal magnitude of 2.5 V and is referenced to the AGND pin on the converter. VREFIN - Voltage input to this pin establishes the voltage reference for the on-chip modulators. IIN+, IIN- - Differential analog input pins for current channel.
Power Supply Connections
Positive Digital Supply Digital Ground Analog Ground Positive Analog Supply 3 4* 13 14
VD+ - The positive digital supply. DGND - Digital Ground. AGND - Analog Ground. VA+ - The positive analog supply.
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CS5466
3. CHARACTERISTICS/SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
Parameter Positive Digital Power Supply Positive Analog Power Supply Voltage Reference Specified Temperature Range Symbol VD+ VA+ VREFIN TA Min 3.135 4.75 -40 Typ 5.0 5.0 2.5 Max 5.25 5.25 +85 Unit V V V C
ANALOG CHARACTERISTICS
* * * Min / Max characteristics and specifications are guaranteed over all Operating Conditions. Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 C. VA+ = VD+ = 5 V 5%; AGND = DGND = 0 V; VREFIN = +2.5 V. All voltages with respect to 0 V. MCLK = 4.096 MHz
*
Parameter
Symbol (Gain = 10) (Gain = 50) (Gain = 100) (Gain = 150) (All Gain Ranges) (All Gain Ranges) {(VIN+)-(VIN-)} IIN
Min 30 2 -
Typ 250 50 25 16.7 25 0.2 0.1
Max 250 -
Unit mV mV mV mV pF k mV pF M %F.S.
Analog Inputs (Current Channel) Differential Input Range {(IIN+)-(IIN-)}
Input Capacitance Effective Input Impedance
CinI ZinI VIN CinV ZinV
Analog Inputs (Voltage Channel) Differential Input Range
Input Capacitance Effective Input Impedance
Accuracy (Energy Outputs) Full-Scale Error
Notes: 1. Applies after system calibration.
(Note 1)
FSE
5
CS5466
ANALOG CHARACTERISTICS (Continued)
Parameter Symbol PSCA PSCD PSCD PC Min 45 75 56 56 56 Typ 1.3 2.9 1.7 21 11.6 55 75 75 75 Max 25 Unit mA mA mA mW mW dB dB dB dB dB
Power Supplies Power Supply Currents
IA+ ID+ (VA+ = VD+ = 5 V) ID+ (VA+ = 5 V, VD+ = 3.3 V) (VA+ = VD+ = 5 V) (VA+ = 5 V, VD+ = 3.3 V)
Power Consumption (Note 2)
Power Supply Rejection Ratio (50, 60 Hz) (Note 3) Voltage Channel (Gain = 10) Current Channel (Gain = 10) (Gain = 50) (Gain = 100) (Gain = 150) Notes: 2. All outputs unloaded. All inputs CMOS level.
3.
PSRR
Definition for PSRR: VREFIN tied to VREFOUT, VA+ = VD+ = 5 V, a 150 mV zero-to-peak sine wave (frequency = 60 Hz) is imposed onto the +5 V supply voltage at VA+ and VD+ pins. The "+" and "-" input pins of both input channels are shorted to VA-. Then the CS5466 is put into an internal test mode and digital output data is collected for the channel under test. The zero-peak value of the digital sinusoidal output signal is determined, and this value is converted into the zero-peak value of the sinusoidal voltage that would need to be applied at the channel's inputs, in order to cause the same digital sinusoidal output. This voltage is then defined as Veq. PSRR is then (in dB): 0.150V PSRR = 20 log ----------------V eq

VOLTAGE REFERENCE
Parameter Symbol REFOUT (Note 4) (Note 5) TCVREF VR VREFIN +2.4 Min +2.4 Typ +2.5 25 6 +2.5 4 25 Max +2.6 60 10 +2.6 Unit V ppm/C mV V pF nA
Reference Output
Output Voltage VREFOUT Temperature Coefficient Load Regulation
Reference Input
Input Voltage Range Input Capacitance Input CVF Current
formula is used to calculate the VREFOUT Temperature Coefficient:.
Notes: 4. The voltage at VREFOUT is measured across the temperature range. From these measurements the following
TCVREF =
5.
AMAX
1 - TAMIN
6
Specified at maximum recommended output current of 1 A, source or sink.
6
(
(
( (VREFOUTMAX - VREFOUTMIN) ( T VREFOUTAVG (
( 1.0 x 10
CS5466
DIGITAL CHARACTERISTICS
* * * *
(Note 6)
Min / Max characteristics and specifications are guaranteed over all Operating Conditions. Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 C. VA+ = VD+ = 5V 5%; AGND = DGND = 0 V. All voltages with respect to 0 V. MCLK = 4.096 MHz
Parameter
Symbol Internal Gate Oscillator (Note 7 and 8) -3 dB VIH XIN RESET MCLK
Min 3 40 40 -
Typ 4.096 -
Max 5 60 60
Unit MHz % % Hz
Master Clock Characteristics
Master Clock Frequency Master Clock Duty Cycle CPUCLK Duty Cycle
Filter Characteristics
High Pass Filter Corner Frequency 0.125 -
Input/Output Characteristics
High-Level Input Voltage (VD+) - 0.5 0.8 VD+ VIL XIN RESET Low-Level Input Voltage (VD = 3.3 V) XIN RESET High-Level Output Voltage (except XOUT) Low-Level Output Voltage (except XOUT) Input Leakage Current Digital Output Pin Capacitance Drive Current FOUT, E1, E2, NEG (Note 9) Iout = +5 mA Iout = -5 mA VOH VOL Iin Cout IDR VIL (VD+) - 1.0 1 5 90 0.3 0.2 VD+ 0.4 10 V V V V A pF mA 1.5 0.2 VD+ V V V V
Low-Level Input Voltage (VD = 5 V)
Notes: 6. All measurements performed under static conditions.
7. 8. 9. If external MCLK is used, then the duty cycle must be between 45% and 55% to maintain this specification. The frequency of CPUCLK is equal to MCLK. VOL and VOH are not specified under this condition.
7
CS5466
SWITCHING CHARACTERISTICS
* * * * Min / Max characteristics and specifications are guaranteed over all Operating Conditions. Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 C. VA+ = 5 V 5% VD+ = 3.3 V 5% or 5 V 5%; AGND = DGND = 0 V. All voltages with respect to 0 V. Logic Levels: Logic 0 = 0 V, Logic 1 = VD+.
Parameter Rise Times (Note 10) Fall Times (Note 10) Any Digital Input Any Digital Output Any Digital Input Any Digital Output
Symbol trise tfall
Min -
Typ 50 50
Max 1.0 1.0 -
Unit s ns s ns
Start-up
Oscillator Start-Up Time XTAL = 4.096 MHz (Note 11) tost 60 ms
E1 and E2 Timing (Note 12 and 13)
Period Pulse Width Rising Edge to Falling Edge E1 Falling Edge to E2 Falling Edge t1 t2 t3 t4 500 250 250 250 ms ms ms ms
FOUT Timing (Note 12 and 13)
Period Pulse Width FOUT low
11.
t5 (Note 14) t6 t7
0.10 -
1 / fFOUT 0.5*t5 0.5*t5 90 -
ms ms ms
Notes: 10. Specified using 10% and 90% points on wave-form of interest. Output loaded with 50 pF.
Oscillator start-up time varies with crystal parameters. This specification does not apply when using an external clock source. 12. Pulse output timing is specified at MCLK = 4.096 MHz. Current and voltage signals are at unity power factor. Refer to Section 5.3 for more information on pulse output pins. 13. Timing is proportional to the frequency of MCLK. 14. When FREQ2 = 0, FREQ1=1 and FREQ0=1, FOUT will have a typical pulse width of 20 s at MCLK = 4.096 MHz.
t1
E1
t2 t4
t3 t1 t2 t3
E2
t5
FOUT
t6
t7
Figure 1. Timing Diagram for E1, E2 and FOUT
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CS5466
ABSOLUTE MAXIMUM RATINGS
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Parameter DC Power Supplies (Notes 15 and 16) Positive Digital Positive Analog (Notes 17, 18, 19) (Note 20) All Analog Pins All Digital Pins Symbol VD+ VA+ IIN IOUT PD VINA VIND TA Tstg Min -0.3 -0.3 - 0.3 -0.3 -40 -65 Typ Max +6.0 +6.0 10 100 500 (VA+) + 0.3 (VD+) + 0.3 85 150 Unit V V mA mA mW V V C C
Input Current, Any Pin Except Supplies Power Dissipation Analog Input Voltage Digital Input Voltage Ambient Operating Temperature Storage Temperature
Output Current, Any Pin Except VREFOUT
Notes: 15. VA+ and AGND must satisfy {(VA+) - (AGND)} + 6.0 V.
16. 17. 18. 19. 20. VD+ and AGND must satisfy {(VD+) - (AGND)} + 6.0 V. Applies to all pins including continuous over-voltage conditions at the analog input pins. Transient current of up to 100 mA will not cause SCR latch-up. Maximum DC input current for a power supply pin is 50 mA. Total power dissipation, including all input currents and output currents.
9
CS5466
IGAIN[1:0] HPF IIN PGA
4th Order Modulator Sinc3 IIR HPF
FREQ[2:0]
Digital Filter
E1
N = 400
Current Channel x VIN 10x
2nd Order Modulator Sinc3 IIR HPF
Energy-toPulse Rate Converter
E2 FOUT NEG
Digital Filter
Voltage Channel
Figure 2. Data Flow
4.
THEORY OF OPERATION
a fixed word rate. The output word is passed to the IIR filter to compensate for the magnitude roll-off of the lowpass filtering operation. An optional digital High-Pass Filter (HPF in Figure 2) removes any dc component from the selected signal path. By removing the dc component from the voltage or current channel, any dc content will also be removed from the calculated average real power as well.
The CS5466 is a dual channel Analog-to-Digital Converter (ADC) followed by a computation engine that performs an energy-to-pulse conversion. The flow diagram for the two data paths is depicted in Figure 2. The analog inputs are structured with two dedicated channels, voltage and current, then optimized to simplify interfacing to sensing elements. The voltage sensing element introduces a voltage waveform on the voltage channel input VIN and is subject to a fixed 10x gain amplifier. A second order deltasigma modulator samples the amplified signal for digitization. Simultaneously, the current sensing element introduces a voltage waveform on the current channel input IIN and is subject to the four selectable gains of the Programmable Gain Amplifier (PGA). The amplified signal is sampled by a fourth order delta-sigma modulator for digitization. Both converters sample at a rate of (MCLK)/8, the over-sampling provides a wide dynamic range and simplified anti-alias filter design.
4.2
Average Real Power Computation
The instantaneous voltage and current data samples are multiplied together to obtain the instantaneous power. The product is then averaged over 400 conversions to compute the average real power value used to drive pulse outputs E1, E2 and FOUT. Output pulse rate of E1 and E2 can be set to one of four frequencies to directly drive a stepper motor or a electromechanical counter or interface to a microcontroller or infrared LED. The alternating output pulses of E1 and E2 allows for use with low cost electromechanical counters. Output FOUT provides a uniform pulse stream that is proportional to the average real power and is designed for system calibration. The FREQ2:0 inputs set the output pulse rate of E1, E2 and FOUT. See Section 5.3 for more details.
4.1
Digital Filters
The decimating digital filters on both channels are Sinc3 filters followed by 4th-order IIR filters. The single bit data is passed to the low pass decimation filter and output at
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CS5466
5.
5.1
FUNCTIONAL DESCRIPTION
Analog Inputs
5.2
High-Pass Filter
The CS5466 is equipped with two fully differential input channels. The inputs VIN and IIN are designated as the voltage and current channel inputs, respectively. The full-scale differential input voltage for the current and voltage channel is 250 mVP.
By removing the offset from either channel, no error component will be generated at dc when computing the average real power. Input pin HPF defines the three options;
5.1.1
Voltage Channel
The output of the line voltage resistive divider or transformer is connected to the VIN+ and VIN- input pins of the CS5466. The voltage channel is equipped with a 10x fixed gain amplifier. The full-scale signal level that can be applied to the voltage channel is 250 mV. If the input signal is a sine wave the maximum RMS voltage is:
250mV 2 P ----------------- 176.78mVRMS
- High-Pass Filter (HPF) is disabled when pin HPF is connected high. - HPF is enabled in the voltage channel when pin HPF is connected low. - HPF is enabled in the current channel when pin HPF is connected to pin FOUT.
5.3
Energy Pulse Outputs
which is approximately 70.7% of maximum peak voltage.
5.1.2
Current Channel
The CS5466 provides three output pins for energy registration. The E1 and E2 pins provide a simple interface from which energy can be registered. These pins are designed to directly connect to a stepper motor or electromechanical counter. The pulse rate on the E1 and E2 pins are in the range of 0 to 4 Hz and all frequency settings are optimized to be used with standard meter constants. The FOUT pin is designated for system calibration, the pulse rate can be selected to reach a frequency of 8000 Hz.
The output of the current sense resistor or transformer is connected to the IIN+ and IIN- input pins of the CS5466. To accommodate different current sensing devices the current channel incorporates a Programmable Gain Amplifier (PGA) that can be set to one of four input ranges. Input pins IGAIN1 and IGAIN0 (See Table 1) define the PGA's four gain selections and corresponding maximum input signal level.
IGAIN1 IGAIN0 Maximum Input Range
5.3.1
Pulse Output Format.
The CS5466 produces alternating pulses on E1 and E2. This pulse format is designed to drive a stepper motor. Each pin produces active low pulses with a minimum pulse width of 250 ms when MCLK = 4.096 MHz. Refer to CS5466 Switching Characteristics on page 8 for timing parameters. The FOUT pin issues active high pulses. The pulse width is equal to 90 ms (typical), unless the period falls below 180 ms. At this time the pulses will be equal to half the period. In mode 3 (FREQ2:0 = 3), the pulse width of all FOUT pulses is typically 20 s regardless of the pulse rate (MCLK = 4.096 MHz).
0 0 1 1
0 1 0 1
250mV 50mV 25mV 16.67mV
10x 50x 100x 150x
5.3.2
Selecting Frequency of E1 and E2
Table 1. Current Channel PGA Setting
For example if IGAIN1=IGAIN0=0, the current channel's PGA gain is set to 10x. If the input signals are pure sinusoids with zero phase shift, the maximum peak differential signal on the current or voltage channel is 250 mVP. The input signal levels are approximately 70.7% of maximum peak voltage producing a full scale energy pulse registration equal to 50% of absolute maximum energy pulse registration. This will be discussed further in Section 5.3.
The pulse rate on E1 and E2 can be set to one of four frequency ranges. Input pins FREQ1 and FREQ0 (See Table 2) determine the maximum frequency on E1 and E2 for pure sinusoidal inputs with zero phase shift. As shown in Figure 1 on page 8, the frequency of E2 is equal to the frequency of E1 with active low alternating pulses. As discussed in Section 5.1.2, the maximum frequency on the E1 and E2 output pins is equal to the selected frequency in Table 2 if the maximum peak differential signal applied to both channels is a sine wave with zero phase shift.
11
CS5466
Table 2. Maximum Frequency for E1, E2 and FOUT Frequency Select FREQ2 FREQ1 FREQ0 Maximum Frequency for a Sine Wave (Notes 1, 2 and 3) E1 or E2 E1+E2 FOUT
0 0 0 0 1 1 1 1
Notes:
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
0.125 Hz 0.25 Hz 0.5Hz 1.0 Hz 0.125 Hz 0.25 Hz 0.5 Hz 1.0 Hz
0.25 Hz 0.5 Hz 1.0 Hz 2.0 Hz 0.25 Hz 0.5 Hz 1.0 Hz 2.0 Hz
64x(E1+E2) 32x(E1+E2) 16x(E1+E2) 2048x(E1+E2) 128x(E1+E2) 64x(E1+E2) 32x(E1+E2) 16x(E1+E2)
16 Hz 16 Hz 16 Hz 4,096 Hz 32 Hz 32 Hz 32 Hz 32 Hz
1 A pure sinusoidal input with zero phase shift is applied to the voltage and current channel. 2 MCLK = 4.096 MHz 3 See Figure 1 on page 8 for E1 and E2 timing diagram.
5.3.3
Selecting Frequency of FOUT
Frequency Select FREQ2 FREQ1 FREQ0
Absolute Max Frequency E1 or E2 E1+E2
The pulse output FOUT is designed to assist with meter calibration. Using the FREQ2:0 pins, FOUT can be set to frequencies higher than that of E1 and E2. The FOUT frequency is directly proportional to the E1 and E2 frequencies. Table 2 defines the maximum frequencies for FOUT and the dependency of FOUT on E1 and E2.
x x
1 1
0 1
1.0 Hz 2.0 Hz
2.0 Hz 4.0 Hz
5.3.4
Absolute Max Frequency on E1 and E2
Table 3. Absolute Max Frequency on E1 and E2
5.3.5
E1 and E2 Frequency Calculation
The CS5466 supports input signals on the voltage and current channel that may not be a sine wave. A typical situation of achieving the absolute maximum frequency on E1 and E2 would be if a 250 mV dc signal is applied to the VIN and IIN input pins. The digital high-pass filter should be disengaged by selecting HPF = 1. The absolute maximum pulse rate observed on E1 and E2, determined by the FREQ2:0 selection is defined below in Table 3.
The pulse output frequency of E1 and E2 is directly proportional to the average power calculated from the input signals. To calculate the output frequency on E1 and E2, use the following transfer function:
VIN * 10 * IIN * IGAIN * FREQmax FREQE1,E2 = -----------------------------------------------------------------------------------------2 VREFIN
Frequency Select FREQ2 FREQ1 FREQ0
Absolute Max Frequency E1 or E2 E1+E2
FREQE1,E2 = Actual frequency of E1 and E2 pulses [Hz] VIN = rms voltage across VIN+ and VIN- [V] IIN = rms voltage across IIN+ and IIN- [V] IGAIN = Current channel gain selection (10, 50, 100, 150) FREQmax = Absolute Max Frequency for E1 and E2 [Hz] VREFIN = Voltage at VREFIN pin [V]
x x
0 0
0 1
0.25 Hz 0.5 Hz
0.5 Hz 1.0 Hz
Table 3. Absolute Max Frequency on E1 and E2 12
CS5466
Example: For a given application, assuming a 50 Hz line frequency and a purely resistive load (unity power factor), the following configuration is used: - FREQ2:0 = 3 FREQmax = 2 Hz - IGAIN1:0 = 2 IGAIN = 100 - VREFIN = VREFOUT = 2.5 V In this configuration the maximum sine wave that can be applied is 250 mVp on the voltage channel and 25 mVp on the current channel. Using the above formula, the output frequency of E1 or E2 is calculated:
5.6
Oscillator Characteristics
XIN and XOUT are the input and output of an inverting amplifier which can provide oscillation and can be configured as an on-chip oscillator, as shown in Figure 3. The oscillator circuit is designed to work with a quartz crystal. To reduce circuit cost, two load capacitors C1
XOUT C1
Oscillator Circuit
.25Vp * 10 * .025Vp * 100 * 2Hz 2 * 2 *2.5V 2
= 1Hz
XIN C2
With maximum pure sinusoidal input signals, the frequency of E1 or E2 is half the absolute maximum frequency set with FREQ2:0. To calculate the frequency of FOUT for the example above, assume FREQ2 = 0.
DGND
C1 = C2 = 22 pF
Figure 3. Oscillator Connection
FOUT = 2048*(E1+E2) = 2048*(2Hz) = 4096Hz
5.4
Energy Direction Indicator
The NEG pin indicates the sign of the calculated average power. If negative average power is detected the NEG output pin will become active high and will remain active high until positive average power is detected. The NEG pin is valid at least 250ns prior to any assertion of E1 or E2, and FOUT, to indicate the sign of a given energy output. The NEG pin is updated at a rate of 10 Hz at MCLK = 4.096 MHz.
and C2 are integrated in the device, one between XIN and DGND, one between XOUT and DGND. Lead lengths should be minimized to reduce stray capacitance. To drive the device from an external clock source, XOUT should be left unconnected while XIN is driven by the external circuitry. There is an amplifier between XIN and the digital section which provides CMOS level signals. This amplifier works with sinusoidal inputs so there are no problems with slow edge times.
5.7
Basic Application Circuit
5.5
Power-on Reset
Upon powering up, the digital circuitry is held in reset until the analog voltage reaches 4.0 V. At that time, an eight XIN clock period delay is enabled to allow the oscillator to stabilize. The CS5466 will then initialize. The device reads the control pins IGAIN1:0, FREQ2:0 and HPF, and begins performing energy measurements.
Figure 4 shows the CS5466 configured to measure power in a single-phase 2-wire system while operating in a single supply configuration. In this diagram, a shunt resistor is used to sense the line current and a voltage divider is used to sense the line voltage. In this type of shunt resistor configuration, the common-mode level of the CS5466 must be referenced to the line side of the power line. This means that the common-mode potential of the CS5466 will track the high voltage levels, as well as low voltage levels, with respect to earth ground potential.
13
CS5466
AGND VA+
9
VD+ RESET EDIR / P4 E2 E1 FOUT NEG FREQ2 FREQ1 FREQ0
VIN+
VIN-
RIR SHUNT RI+
IGAIN0 IHPF XOUT
21
VREFIN XIN VREFOUT CPUCLK AGND VA31 42
Figure 4. Typical Connection Diagram
14
8
0.1 F
DGND
1
2
5
IIN+
IGAIN1
7
CI+
CIdiff
61
32
CI-
02
Calibration Resistor
IIN-
6 81
R2
71
8
51
01
R1
R V-
CV-
12
CVdiff
22
CV+
3
41
11
L
470 nF
120 VAC
N
500
500 + 470 F 0.1 F
10 10 k 1 F +
0.1F
Stepper Motor
5466 Config. Settings
4.096 MHz
Note: Indicates common (floating) return.
CS5466
6. PACKAGE DIMENSIONS
24L SSOP PACKAGE DRAWING
N
D
E11 A2 A1 A
E
L
e
b2 SIDE VIEW
END VIEW
SEATING PLANE
123
TOP VIEW
DIM A A1 A2 b D E E1 e L
MIN -0.002 0.064 0.009 0.311 0.291 0.197 0.022 0.025 0
INCHES NOM -0.006 0.068 -0.323 0.307 0.209 0.026 0.03 4
MAX 0.084 0.010 0.074 0.015 0.335 0.323 0.220 0.030 0.041 8
MIN -0.05 1.62 0.22 7.90 7.40 5.00 0.55 0.63 0
MILLIMETERS NOM -0.13 1.73 -8.20 7.80 5.30 0.65 0.75 4
NOTE MAX 2.13 0.25 1.88 0.38 8.50 8.20 5.60 0.75 1.03 8
2,3 1 1
JEDEC #: MO-150
Controlling Dimension is Millimeters. Notes: 1. "D" and "E1" are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension "b" does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of "b" dimension at maximum material condition. Dambar intrusion shall not reduce dimension "b" by more than 0.07 mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
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CS5466
7. REVISIONS
Date September 2004 October 2004 Initial Release Corrected table heading on Page 6. Changes PP1 PP2
Revision
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com
IMPORTANT NOTICE "Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS (INCLUDING MEDICAL DEVICES, AIRCRAFT SYSTEMS OR COMPONENTS AND PERSONAL OR AUTOMOTIVE SAFETY OR SECURITY DEVICES). INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.
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